(a) Field of the Invention The present invention relates to a method of manufacturing a flash memory. More particularly, the present invention relates to a method of manufacturing an isolation layer of a flash memory, in which source resistance can be reduced by using an isolation layer having an STI (Shallow Trench Isolation) structure.
(b) Description of the Related Art
Generally, a NOR type of flash memory uses a common source scheme, and one source contact is formed per 16 cells.
In addition, an STI technique has recently been used for forming an isolation layer in a semiconductor device so as to reduce a cell size. Moreover, in the case of a flash memory having a scale of 0.35 μm or less, an SAS (Self Aligned Source) technique is used for reducing a gap between a gate and a common source line.
A method of manufacturing a flash memory using such STI and SAS techniques may be found in Korean Patent Publication No. 2004-60550.
FIG. 1A is a top plan view and FIG. 1B is a cross-sectional view showing a structure of a flash memory cell manufactured by STI and SAS techniques.
As shown in FIG. 1A and FIG. 1B, a common source region 12 is formed in a line shape by ion-implanting N-type dopants into a semiconductor substrate 10, which includes a plurality of STI isolation layers 14 formed in parallel with a bit line 18 and active regions formed between the STI isolation layers 14. Here, reference numerals 16 and 20 respectively denote a gate line and a contact electrode. However, since a line of the common source region 12 is formed in generally a square wave shape along surfaces of STI isolation layers 14 and active regions, source resistance of a flash memory cell may be significantly increased.
As shown in FIG. 2, the significant increase in source resistance is mainly caused because an actual surface resistance is formed over a wider area since the source resistance is formed along the trench surface of the STI isolation layer 14, and also because resistivity of a sidewall of the trench is high since a relatively small amount of dopant is implanted therein.
Moreover, it is notable that the trench depth of an STI isolation layer tends to be increased since a flash memory device uses a high internal voltage, and that, accordingly, the trench is formed with a smaller depth in a cell region than in a peripheral circuit region so as to prevent source resistance in the cell region from being affected by the increase in the trench depth.
However, according to a conventional method of manufacturing an STI isolation layer of a flash memory cell, a forming process of an etch mask and an etching process for trenches should be performed separately in order to form trenches having different depths on a cell region and a peripheral circuit region. Therefore, a manufacturing process may become complicated and manufacturing costs may also be increased.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form part of the prior art with respect to the present invention.